The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2005
Filed:
Apr. 27, 2004
Lionel J. D'luna, Irvine, CA (US);
Mark Chambers, Mission Viejo, CA (US);
Thomas Hughes, Dana Point, CA (US);
Kwang Y. Kim, Irvine, CA (US);
Sathish K. Radhakrishnan, Karnataka, IN;
Lionel J. D'Luna, Irvine, CA (US);
Mark Chambers, Mission Viejo, CA (US);
Thomas Hughes, Dana Point, CA (US);
Kwang Y. Kim, Irvine, CA (US);
Sathish K. Radhakrishnan, Karnataka, IN;
Broadcom Corporation, Irvine, CA (US);
Abstract
A system and method are used to allow high speed communication between a chip and an external device. The system and method include a PLL with multiple phased outputs configured to be controlled digitally, a deskew PLL configured to align a clock of controller circuitry to interface circuitry, and a phase interpolated voltage controlled delay line configured to phase shift incoming signals. Analog design techniques of phase interpolation accurately position clocks and strobe signals that are required for high speed interfaces. The high speed interface is for transmitting and receiving signals from the external device, for example, a DDR DRAM.