Voltage discharge technique for controlling threshold-voltage characteristics of floating-gate transistor in circuitry such as flash eprom

Abstract

An operation, typically an erasure operation, is performed on a floating-gate FET () whose components include a body region (BR) and a control-gate electrode (CG) above a floating-gate electrode (FG). A first body voltage (V) at a body node (N) is converted into a second body voltage (V) applied to the body region. A first control voltage (V) at a control node (N) is converted into a second control voltage (V) applied to the control-gate electrode. The two first voltages are placed at respective conditioning values such that the two second voltages cause the FET to be in a specified condition, typically an erased condition. The two first voltages are subsequently discharged with the body and control nodes electrically connected to each other at least as the discharging begins. The two first voltages thereby begin discharging largely simultaneously. This avoids FET damage.