The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 13, 2005

Filed:

May. 27, 2004
Applicants:

Victor Wing Chung Chan, New Paltz, NY (US);

Hsing-jen C. Wann, Carmel, NY (US);

Shih-fen Huang, Bedford Corners, NY (US);

Oleg Gluschenkov, Poughkeepsie, NY (US);

Inventors:

Victor Wing Chung Chan, New Paltz, NY (US);

Hsing-Jen C. Wann, Carmel, NY (US);

Shih-Fen Huang, Bedford Corners, NY (US);

Oleg Gluschenkov, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K017/16 ;
U.S. Cl.
CPC ...
Abstract

A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.


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