The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 13, 2005
Filed:
Dec. 27, 2001
Angela Hui, Fremont, CA (US);
Shenqing Fang, Sunnyvale, CA (US);
Hiroyuki Kinoshita, Sunnyvale, CA (US);
Kelwin Ko, San Jose, CA (US);
Wenmei LI, Sunnyvale, CA (US);
Yu Sun, Saratoga, CA (US);
Hiroyuki Ogawa, Sunnyvale, CA (US);
Chi Chang, Redwood City, CA (US);
Angela Hui, Fremont, CA (US);
Shenqing Fang, Sunnyvale, CA (US);
Hiroyuki Kinoshita, Sunnyvale, CA (US);
Kelwin Ko, San Jose, CA (US);
Wenmei Li, Sunnyvale, CA (US);
Yu Sun, Saratoga, CA (US);
Hiroyuki Ogawa, Sunnyvale, CA (US);
Chi Chang, Redwood City, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Spansion LLC, , JP;
Abstract
A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.