The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2005
Filed:
Jun. 06, 2002
Luu Thanh Nguyen, Sunnyvale, CA (US);
Ken Pham, San Jose, CA (US);
Peter Deane, Los Altos, CA (US);
William Paul Mazotti, San Martin, CA (US);
Bruce Carlton Roberts, San Jose, CA (US);
Hau Thanh Nguyen, San Jose, CA (US);
John P. Briant, Cambridge, GB;
Roger Clarke, Cambridge, GB;
Michael R. Nelson, Cambridge, GB;
Janet E. Townsend, Fulbourn, GB;
Luu Thanh Nguyen, Sunnyvale, CA (US);
Ken Pham, San Jose, CA (US);
Peter Deane, Los Altos, CA (US);
William Paul Mazotti, San Martin, CA (US);
Bruce Carlton Roberts, San Jose, CA (US);
Hau Thanh Nguyen, San Jose, CA (US);
John P. Briant, Cambridge, GB;
Roger Clarke, Cambridge, GB;
Michael R. Nelson, Cambridge, GB;
Janet E. Townsend, Fulbourn, GB;
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
The techniques of the present invention are directed towards setting a photonic device into a groove of a substrate, which is then attached to the chip sub-assembly in a way that the resulting optoelectronic package has a low profile and the interconnects between the photonic device and the semiconductor chip are short. The technique involves partially etching a groove in a substrate to allow for positioning of a photonic device within the groove. The photonic device is connected to the chip sub-assembly through interconnects that extend through the thickness of the substrate. The photonic devices are placed on their sides so that the active facets are perpendicular to the main axis of the chip sub-assembly. In this configuration, the optical fibers can be positioned parallel to the CSA top surface, ensuring a low module profile in the process.