The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 06, 2005
Filed:
Mar. 09, 2004
Hung Q. Nguyen, Fremont, CA (US);
Steve Choi, Irvine, CA (US);
Loc Hoang, San Jose, CA (US);
Alexander Kotov, Sunnyvale, CA (US);
Hung Q. Nguyen, Fremont, CA (US);
Steve Choi, Irvine, CA (US);
Loc Hoang, San Jose, CA (US);
Alexander Kotov, Sunnyvale, CA (US);
Silicon Storage Technology, Inc., Sunnyvale, CA (US);
Abstract
A circuit to screen for defects in an addressable line in a non-volatile memory array comprises a current mirror circuit which has a plurality of mirroring stages. The current mirror circuit is connected to the addressable line and receives a control signal and mirrors the control signal to provide a current to the addressable line. In a preferred embodiment, the current mirror circuit provides a high voltage current to the addressable line which is used to effectuate an operation such as program or erase to the memory cells connected to the addressable line. The change in state or the absence of change in state of the memory cells connected to the addressable line can be used to screen for defects in the addressable line.