The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2005

Filed:

Sep. 18, 2002
Applicants:

Gin Yee, Sunnyvale, CA (US);

Pradeep Trivedi, Sunnyvale, CA (US);

Sudhakar Bobba, Sunnyvale, CA (US);

Inventors:

Gin Yee, Sunnyvale, CA (US);

Pradeep Trivedi, Sunnyvale, CA (US);

Sudhakar Bobba, Sunnyvale, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F017/50 ; G06F009/45 ;
U.S. Cl.
CPC ...
Abstract

A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for performing timing analysis on an integrated circuit partitioned into voltage drop regions is provided. During the timing analysis, a set of logic paths segments in each voltage drop region is tested to ensure that the integrated circuit meets a set of predefined timing requirements. Logic path segments that reside in different voltage drop regions are tested using a supply voltage inputted by the respective voltage drop region.


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