The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 29, 2005

Filed:

Apr. 02, 2002
Applicants:

Kiyohito Iljima, Nirasaki, JP;

Seiichi Kaise, Nirasaki, JP;

Keiko Takahashi, Nirasaki, JP;

Akira Obi, Nirasaki, JP;

Inventors:

Kiyohito Iljima, Nirasaki, JP;

Seiichi Kaise, Nirasaki, JP;

Keiko Takahashi, Nirasaki, JP;

Akira Obi, Nirasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F007/00 ;
U.S. Cl.
CPC ...
Abstract

At a time Tp when a wafer W is transferred into either a load lock chamber LLor LL, periods PSL for the load lock chambers LLand LLto get ready to permit a transfer of a next wafer W thereinto are calculated based on a timing for exchange of wafers W between the load lock chamber LLor LLand a loader module LM. When the periods PSL are calculated, a loader arm LAor LAselects a next wafer W having the shortest period to get ready to be transferable into the load lock chamber LLor LL, from load ports LPto LP. This improves transfer delay in a cluster tool provided with the load lock chambers.


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