The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2005
Filed:
Dec. 30, 2003
Bheem Patel, Sunnyvale, CA (US);
Ming Zeng, Arcadia, CA (US);
Tsung-chuan Whang, Cupertino, CA (US);
Bheem Patel, Sunnyvale, CA (US);
Ming Zeng, Arcadia, CA (US);
Tsung-Chuan Whang, Cupertino, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.