The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2005
Filed:
Sep. 18, 2003
Applicant:
Edward E. Miller, Beaverton, OR (US);
Inventor:
Edward E. Miller, Beaverton, OR (US);
Assignee:
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K005/22 ;
U.S. Cl.
CPC ...
Abstract
Comparator circuits, including rail-to-rail comparator circuits, can implement inverter structures such as current-starved inverters to provide hysteresis to the comparator's output. For example, a current-starved inverter can have its input driven by the comparator output and add current to the currents produced by the comparator's input stage. The inverter current can be derived from bias sources used to bias the input stage of the comparator so that the inverter current can track the input stage bias currents.