The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 29, 2005
Filed:
Sep. 06, 2001
Yohei Akita, Kokubunji, JP;
Naoki Kato, Kodaira, JP;
Kazuo Yano, Hino, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
There is provided a logic circuit causing the same delay time as a conventional logic circuit and acting as a D flip-flop circuit with a data-selecting function. A logic circuit having the circuitry shown in FIG.will be described briefly. Two transmission gates TG(TG) and TGand two inverters IVand IVare used to define a data propagation path from an input port I(I) to an output port O. Thus, four logic gates are located along the path in the same manner as they are in a conventional D flip-flop circuit. The transmission gate TG(TG) is controlled using a NOR circuitthat inputs a clock CLK and a select signal /sel that is the reverse of a select signal sel (NOR circuitthat inputs the clock CLK and the select signal sel). The transmission gate TGis controlled with the clock CLK. Either of two input data items is selected based on the select signals, and then output. When a D flip-flop circuit with a data-selecting function that causes the same delay time as a conventional D flip-flop circuit is adapted to a pipeline circuit, the action of the pipeline circuit can be speeded up.