The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 22, 2005
Filed:
Oct. 29, 2003
Jürgen Amon, Dresden, DE;
Jürgen Faul, Radebeul, DE;
Ulrike Gruening, München, DE;
Frank Jakubowski, Dresden, DE;
Thomas Schuster, Dresden, DE;
Rudolf Strasser, Hsin Chu, TW;
Jürgen Amon, Dresden, DE;
Jürgen Faul, Radebeul, DE;
Ulrike Gruening, München, DE;
Frank Jakubowski, Dresden, DE;
Thomas Schuster, Dresden, DE;
Rudolf Strasser, Hsin Chu, TW;
Infineon Technologies AG, München, DE;
Abstract
The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS, GS, GS, GS) on a semiconductor substrate (), having the following steps: application of the gate stacks (GS, GS, GS, GS) to a gate dielectric () above the semiconductor substrate (); formation of a sidewall oxide () on sidewalls of the gate stacks (GS, GS, GS, GS); application and patterning of a mask () on the semiconductor structure; and implantation of a contact doping () in a self-aligned manner with respect to the sidewall oxide () of the gate stacks (GS, GS) in regions not covered by the mask ().