The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2005
Filed:
Sep. 30, 2003
John Connor, Burlington, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Christopher S. Putnam, Hinesburg, VT (US);
Alan L. Roberts, Jericho, VT (US);
John Connor, Burlington, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Christopher S. Putnam, Hinesburg, VT (US);
Alan L. Roberts, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An ESD protection circuit including the following: one or more inverters (I, I, I), each of the one or more inverters having an input and an output; an RC network () having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N) joined with the output of at least one of one or more inverters (I, I, I); and a feedback device (NKP) in communication with clamping device (N) and output node (RCT) of RC network (). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I, I, I) includes a PFET and NFET pair (P/N, P/N, P/N).