The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 15, 2005
Filed:
May. 02, 2002
Applicants:
Sundar Narayanan, Santa Clara, CA (US);
Chidambaram Kallingal, San Jose, CA (US);
Inventors:
Sundar Narayanan, Santa Clara, CA (US);
Chidambaram Kallingal, San Jose, CA (US);
Assignee:
Cypress Semiconductor Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/302 ;
U.S. Cl.
CPC ...
Abstract
A method of making a semiconductor structure includes trimming a patterned hard mask with a wet etch, wherein the hard mask is on a gate layer; and etching the gate layer. In making multiple structures on a semiconductor wafer, an average width of lines in the patterned hard mask is trimmed by at least 100 Å.
Narayanan, Sundar. (2005). Method of forming a narrow gate, and product produced thereby (U.S. Patent No. 6964929). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6964929
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile