The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
May. 31, 2002
Kevin M. Hill, Folsom, CA (US);
Chris D. Matthews, Sacramento, CA (US);
Amir A. Bashir, El Dorado Hills, CA (US);
Kevin E. Arendt, Folsom, CA (US);
Andrew M. Volk, Granite Bay, CA (US);
Kevin M. Hill, Folsom, CA (US);
Chris D. Matthews, Sacramento, CA (US);
Amir A. Bashir, El Dorado Hills, CA (US);
Kevin E. Arendt, Folsom, CA (US);
Andrew M. Volk, Granite Bay, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention relate to a memory control hub (MCH) clock master of an MCH. Typically, in a computer system, a processor is coupled to the MCH by a front-side bus (FSB). Further, an input/output control hub (ICH) is typically coupled to the MCH by a back-side bus or Hub Link. In one embodiment, a host phase locked loop (HPLL) of the MCH clock master receives an FSB clock signal transmitted on the FSB and generates a local synchronous clock signal based upon the FSB clock signal. A delayed lock loop (DLL) of the MCH clock master also receives the FSB clock signal and generates a system clock signal. Particularly, the DLL synchronizes the system clock signal to the local synchronous clock and drives the system clock signal to many different devices on the board.