The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Aug. 05, 2003
Applicants:
Somnath S. Nag, Plano, TX (US);
Girish A. Dixit, Plano, TX (US);
Srikanth Krishnan, Richardson, TX (US);
Inventors:
Somnath S. Nag, Plano, TX (US);
Girish A. Dixit, Plano, TX (US);
Srikanth Krishnan, Richardson, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L021/31 ;
U.S. Cl.
CPC ...
Abstract
A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition () followed by high capacitively-coupled RF bias for planarizing deposition () limits the charge build up on the underlying structure ().