The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 08, 2005
Filed:
Jan. 15, 2004
Hideaki Masuda, Kanagawa-ken, JP;
Hideshi Miyajima, Kanagawa-ken, JP;
Rempei Nakata, Kanagawa-ken, JP;
Hideaki Masuda, Kanagawa-ken, JP;
Hideshi Miyajima, Kanagawa-ken, JP;
Rempei Nakata, Kanagawa-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench. The first non-porous film includes a first layer has a high etching selectivity ratio relative to the protective film, and a second layer has a high etching selectivity ratio relative to the resist mask and the second porous film.