The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 08, 2005

Filed:

Aug. 14, 2003
Applicants:

Katsuya Furue, Hyogo, JP;

Shigeru Kikuda, Hyogo, JP;

Kiyohiro Furutani, Hyogo, JP;

Tetsushi Tanizaki, Hyogo, JP;

Shigehiro Kuge, Hyogo, JP;

Takashi Kono, Hyogo, JP;

Inventors:

Katsuya Furue, Hyogo, JP;

Shigeru Kikuda, Hyogo, JP;

Kiyohiro Furutani, Hyogo, JP;

Tetsushi Tanizaki, Hyogo, JP;

Shigehiro Kuge, Hyogo, JP;

Takashi Kono, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/66 ;
U.S. Cl.
CPC ...
Abstract

A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.


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