The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2005
Filed:
Sep. 17, 2003
Francois Ibrahim Atallah, Raleigh, NC (US);
James Norris Dieffenderfer, Apex, NC (US);
Jeffrey H. Fischer, Cary, NC (US);
Michael Thomas Fragano, Essex Junction, VT (US);
Daniel Stephen Geise, South Burlington, VT (US);
Jeffery Howard Oppold, Richmond, VT (US);
Michael R. Ouellette, Westford, VT (US);
Neelesh Govindaraya Pai, Williston, VT (US);
William Robert Reohr, Ridgefield, CT (US);
Joel Abraham Silberman, Somers, NY (US);
Thomas Philip Speier, Holly Springs, NC (US);
Francois Ibrahim Atallah, Raleigh, NC (US);
James Norris Dieffenderfer, Apex, NC (US);
Jeffrey H. Fischer, Cary, NC (US);
Michael Thomas Fragano, Essex Junction, VT (US);
Daniel Stephen Geise, South Burlington, VT (US);
Jeffery Howard Oppold, Richmond, VT (US);
Michael R. Ouellette, Westford, VT (US);
Neelesh Govindaraya Pai, Williston, VT (US);
William Robert Reohr, Ridgefield, CT (US);
Joel Abraham Silberman, Somers, NY (US);
Thomas Philip Speier, Holly Springs, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A random access memory circuit comprises a plurality of memory cells and at least one decoder coupled to the memory cells, the decoder being configurable for receiving an input address and for accessing one or more of the memory cells in response thereto. The random access memory circuit further comprises a plurality of sense amplifiers operatively coupled to the memory cells, the sense amplifiers being configurable for determining a logical state of one or more of the memory cells. A controller coupled to at least a portion of the sense amplifiers is configurable for selectively operating in at least one of a first mode and a second mode. In the first mode of operation, the controller enables one of the sense amplifiers corresponding to the input address and disables the sense amplifiers not corresponding to the input address. In the second mode of operation, the controller enables substantially all of the sense amplifiers. The memory circuit advantageously provides an adaptable latency by controlling the mode of operation of the circuit.