Ram memory circuit having a plurality of banks and an auxiliary device for testing

Abstract

One embodiment of the invention provides a RAM memory circuit having k≧2 banks, each of which having a multiplicity of memory cells and a selection device to simultaneously select groups of in each case n≧2 memory cells of the bank for the writing or reading of n parallel data. For the fast testing of all the banks, devices are included for the parallel switching of the banks such that reading and writing may be effected simultaneously at all the banks. For each bank, a dedicated evaluation device is included for comparing the n data respectively read out at the relevant bank with a reference information item, which is representative of the write data which have previously been written in at the currently selected memory cell group of the bank, and for providing a result information item, comprising 1≦m≦n/k bits, each of which indicates whether a subset precisely assigned to it from m subsets of the n read data corresponds to a part of the reference information item which is precisely assigned to said subset.