The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 01, 2005
Filed:
May. 22, 2003
Applicant:
Masahiko Ishiwaki, Hyogo, JP;
Inventor:
Masahiko Ishiwaki, Hyogo, JP;
Assignee:
Renesas Technology Corp., Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L007/00 ;
U.S. Cl.
CPC ...
Abstract
A reference clock signal or a clock signal delayed in phase from the clock signal by π/2 is input to D input terminal of a flip-flop circuit. An FSM receives signals input to the flip-flop circuits and signals which have been held by the flip-flop circuits, and outputs an up signal and a down signal. The flip-flop circuits and the FSM operate in synchronization only with a rising edge of a data signal.
Ishiwaki, Masahiko. (2005). Frequency detector detecting variation in frequency difference between data signal and clock signal (U.S. Patent No. 6960960). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6960960
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile