The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 01, 2005

Filed:

Oct. 30, 2003
Applicants:

Emanuele Confalonieri, Milan, IT;

Marco Sforzin, Cantu', IT;

Carla Poidomani, Cassina de' Pecchi, IT;

Carlo Lisi, Milan, IT;

Inventors:

Emanuele Confalonieri, Milan, IT;

Marco Sforzin, Cantu', IT;

Carla Poidomani, Cassina de' Pecchi, IT;

Carlo Lisi, Milan, IT;

Assignee:

STMicroelectronics S.r.l., Agrate Brianza, IT;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K003/17 ;
U.S. Cl.
CPC ...
Abstract

A circuit for detecting a logic transition is proposed. The circuit includes an input terminal for receiving a logic signal, an output terminal for generating a detection signal, two capacitors, in a steady condition a first one of the capacitors and a second one of the capacitors being alternately at a first voltage and at a second voltage, respectively, and exchanging means for bringing the first capacitor to the second voltage and the second capacitor to the first voltage in response to a switching of the logic signal; the circuit further includes means for maintaining a command node at the first voltage in the steady condition, means for generating a reset pulse through the first capacitor in response to the switching, means for bringing the command node to the second voltage in response to the reset pulse, a generator of regulated current for bringing back the command node to the first voltage through the second capacitor, and logic means having a regulated threshold voltage comprised between the first and the second voltage, the logic means asserting the detection signal when the command node is brought to the second voltage and deasserting the detection signal when the command node reaches the threshold voltage.


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