The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 11, 2005
Filed:
Nov. 27, 2002
N. Johan Knall, Sunnyvale, CA (US);
Roy E. Scheuerlein, Cupertino, CA (US);
James M. Cleeves, Redwood City, CA (US);
Bendik Kleveland, Santa Clara, CA (US);
Mark G. Johnson, Los Altos, CA (US);
N. Johan Knall, Sunnyvale, CA (US);
Roy E. Scheuerlein, Cupertino, CA (US);
James M. Cleeves, Redwood City, CA (US);
Bendik Kleveland, Santa Clara, CA (US);
Mark G. Johnson, Los Altos, CA (US);
Matrix Semiconductor, Inc., Santa Clara, CA (US);
Abstract
The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.