The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2005
Filed:
Mar. 30, 2001
Girish P. Ramanathan, Ranco Cordova, CA (US);
Srinivasan T. Rajappa, Folsom, CA (US);
Girish P. Ramanathan, Ranco Cordova, CA (US);
Srinivasan T. Rajappa, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A system for measuring timing margins in an interface between a core and an input/output device on a chipset. In order to measure the amount of available variation in data and strobe signals, delay lines are introduced so that the data and strobe signals may be varied in relation to each other. By incrementally changing the delay and hence the time difference between the two signals, it is possible to determine the allowable variation when the device fails to operate. By providing delays on both sides, it is possible to determine the timing margin on both the setup and hold of the signals.