The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 04, 2005
Filed:
Dec. 18, 2002
Applicants:
Shahram Jamshidi, Cupertino, CA (US);
Sudarshan Kumar, Fremont, CA (US);
Inventors:
Shahram Jamshidi, Cupertino, CA (US);
Sudarshan Kumar, Fremont, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/096 ;
U.S. Cl.
CPC ...
Abstract
A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.
Jamshidi, Shahram. (2005). Gate-clocked domino circuits with reduced leakage current (U.S. Patent No. 6952118). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6952118
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile