The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 27, 2005
Filed:
Dec. 09, 2003
Yuezhen Fan, San Jose, CA (US);
Jason Xu, San Jose, CA (US);
Stephen Wing-ho Tang, San Jose, CA (US);
Zhi-min Ling, Cupertino, CA (US);
Yuezhen Fan, San Jose, CA (US);
Jason Xu, San Jose, CA (US);
Stephen Wing-Ho Tang, San Jose, CA (US);
Zhi-Min Ling, Cupertino, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.