The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2005

Filed:

Dec. 29, 2003
Applicants:

Alec W. Smidt, Folsom, CA (US);

Andrew D. Proescholdt, Rancho Cordova, CA (US);

Boubekeur Benhamida, El Dorado Hills, CA (US);

Ravi Annavajjhala, Folsom, CA (US);

Inventors:

Alec W. Smidt, Folsom, CA (US);

Andrew D. Proescholdt, Rancho Cordova, CA (US);

Boubekeur Benhamida, El Dorado Hills, CA (US);

Ravi Annavajjhala, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C016/06 ;
U.S. Cl.
CPC ...
Abstract

A high-speed voltage level shifter. A transistor () may be connected to high voltage (VPP) and may act as a source of a limited current to a first node (), and a driver () connected to the first node may provide a level-shifted output signal (VOUT) to a memory control input line of a memory cell (). A plurality of series-connected transistors (A–N) may be connected between a second node (A) and a circuit ground, each transistor may have an input connected to a corresponding control signal (VIN-A to VIN-N) from a control circuit (). A transistor () may be connected between the first node and the second node in a source-follower configuration and may have an input connected to a bias voltage (VBIAS) which may limit the voltage at nodeA, so transistorsA–N may be low-voltage, high speed transistors.


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