The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 20, 2005

Filed:

Mar. 19, 2003
Applicant:

Henry Chung, Taipei, TW;

Inventor:

Henry Chung, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/302 ;
U.S. Cl.
CPC ...
Abstract

A patterning method for fabricating integrated circuits. The method includes forming a material layer over a substrate and then forming a photoresist layer over the material layer. The photoresist layer has a thickness small enough to relax the limitations when the photoresist layer is patterned in a photolithographic process. A shroud liner is formed over the photoresist layer such that height of the shroud liner is significantly greater than width of the shroud liner. Thereafter, the shroud liner undergoes a processing treatment to remove the sections attached to the sidewalls of the photoresist layer. Using the remaining shroud liner as an etching mask, an etching operation is carried out to pattern the material layer.


Find Patent Forward Citations

Chung, Henry. (2005). Patterning method for fabricating integrated circuit (U.S. Patent No. 6946400). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6946400

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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