The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2005

Filed:

Dec. 20, 2002
Applicants:

John G Rohrbaugh, Ft Collins, CO (US);

Jeff Rearick, Ft Collins, CO (US);

Christopher M Juenemann, Aurora, CO (US);

Inventors:

John G Rohrbaugh, Ft Collins, CO (US);

Jeff Rearick, Ft Collins, CO (US);

Christopher M Juenemann, Aurora, CO (US);

Assignee:

Agilent Technologies, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F017/50 ;
U.S. Cl.
CPC ...
Abstract

A system and method for evaluating a device under test (DUT) that utilizes a model of the DUT interfaced to DUT interface logic, which is designed to interface the DUT to automated testing equipment (ATE). By ensuring that the model includes a description of the DUT and of the DUT testing interface, conditions such as connections between ports of the IC (i.e., buddying) that may or may not be interfaced to the ATE may be included in the model to enable precise test pattern sets to be generated using the model. The test pattern sets may be used by a simulator to test the design of an IC or by ATE to test a fabricated IC having the design.


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