The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Aug. 06, 2002
Andrew W. Lai, Fremont, CA (US);
Randy J. Simmons, San Jose, CA (US);
Teymour M. Mansour, Sunnyvale, CA (US);
Vincent L. Tong, Fremont, CA (US);
Jeffrey V. Lindholm, Longmont, CO (US);
Jay T. Young, Louisville, CO (US);
William R. Troxel, Longmont, CO (US);
Sridhar Krishnamurthy, San Jose, CA (US);
Andrew W. Lai, Fremont, CA (US);
Randy J. Simmons, San Jose, CA (US);
Teymour M. Mansour, Sunnyvale, CA (US);
Vincent L. Tong, Fremont, CA (US);
Jeffrey V. Lindholm, Longmont, CO (US);
Jay T. Young, Louisville, CO (US);
William R. Troxel, Longmont, CO (US);
Sridhar Krishnamurthy, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.