The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2005

Filed:

Aug. 30, 2001
Applicants:

Hiroyuki Takahashi, Kanagawa, JP;

Atsushi Nakagawa, Kanagawa, JP;

Yoshiyuki Katou, Kanagawa, JP;

Hideo Inaba, Kanagawa, JP;

Noriaki Komatsu, Kanagawa, JP;

Takuya Hirota, Kanagawa, JP;

Masahiro Yoshida, Kanagawa, JP;

Inventors:

Hiroyuki Takahashi, Kanagawa, JP;

Atsushi Nakagawa, Kanagawa, JP;

Yoshiyuki Katou, Kanagawa, JP;

Hideo Inaba, Kanagawa, JP;

Noriaki Komatsu, Kanagawa, JP;

Takuya Hirota, Kanagawa, JP;

Masahiro Yoshida, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C007/00 ;
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S, Sare divided into respective four blocks B˜Band B˜B. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.


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