The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2005

Filed:

Mar. 26, 2004
Applicants:

Thomas Rueckes, Boston, MA (US);

Brent M. Segal, Woburn, MA (US);

Bernhard Vogeli, Boston, MA (US);

Darren K. Brock, Elmsford, NY (US);

Venkatachalam C. Jaiprakash, Fremont, CA (US);

Claude L. Bertin, South Burlington, VT (US);

Inventors:

Thomas Rueckes, Boston, MA (US);

Brent M. Segal, Woburn, MA (US);

Bernhard Vogeli, Boston, MA (US);

Darren K. Brock, Elmsford, NY (US);

Venkatachalam C. Jaiprakash, Fremont, CA (US);

Claude L. Bertin, South Burlington, VT (US);

Assignee:

Nantero, Inc., Woburn, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C011/34 ;
U.S. Cl.
CPC ...
Abstract

A non-volatile memory array includes a plurality of memory cells, each cell receiving a bit line, word line, and release line. Each memory cell includes a cell selection transistor and a restore transistor with first, second and third nodes. Each cell further includes an electromechanically deflectable switch, the position of which manifests the logical state of the cell. Each cell is bit selectable for read and write operations.


Find Patent Forward Citations

Loading…