The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2005

Filed:

Sep. 25, 2003
Applicants:

William B. Andrews, Emmaus, PA (US);

Mou C. Lin, High Bridge, NJ (US);

Harold Scholz, Allentown, PA (US);

Arifur Rahman, Yonkers, NY (US);

Inventors:

William B. Andrews, Emmaus, PA (US);

Mou C. Lin, High Bridge, NJ (US);

Harold Scholz, Allentown, PA (US);

Arifur Rahman, Yonkers, NY (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K019/177 ;
U.S. Cl.
CPC ...
Abstract

A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).


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