The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Apr. 12, 2002
Laura Pressley, Austin, TX (US);
David E. Brown, Austin, TX (US);
Travis Lewis, Austin, TX (US);
Edward E. Ehrichs, Austin, TX (US);
Paul R. Besser, Sunnyvale, CA (US);
Laura Pressley, Austin, TX (US);
David E. Brown, Austin, TX (US);
Travis Lewis, Austin, TX (US);
Edward E. Ehrichs, Austin, TX (US);
Paul R. Besser, Sunnyvale, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method and system to locate and detect voids in films that are involved in critical dimension (CD) structures and non-critical dimension structures in semiconductor devices are presented. One or more test structures (resolution devices) are formed on a semiconductor wafer. A scanning electron microscope is operated in voltage contrast mode to obtain a digital representation of the test structure. The voltage contrast image of the test structure is then analyzed with a system which automates the location, identification, and categorization of voids in the test structure. Additionally, the method is more sensitive to electrical marginalities caused by voids than other wafer electrical testing methods. The method is suitable inline monitoring during a manufacturing process by utilizing the automation of void identification, location, and categorization as a process monitoring parameter.