The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 13, 2005
Filed:
Oct. 30, 2003
Takeshi Uchihara, Saitama, JP;
Yasunori Usui, Kanagawa, JP;
Hideyuki Ura, Kanagawa, JP;
Takuma Hara, Kanagawa, JP;
Takeshi Uchihara, Saitama, JP;
Yasunori Usui, Kanagawa, JP;
Hideyuki Ura, Kanagawa, JP;
Takuma Hara, Kanagawa, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
According to the present invention, there is provided a semiconductor device having, a semiconductor substrate having a surface on which an insulating layer is formed, a first-conductivity-type first semiconductor layer formed on the insulating layer and having a first impurity concentration, a first-conductivity-type second semiconductor region formed in the first semiconductor layer from a surface of the first semiconductor layer to a surface of the insulating layer, and having a concentration higher than the first impurity concentration, a second-conductivity-type third semiconductor region formed in the first semiconductor layer from the surface of the first semiconductor layer to the surface of the insulating layer with a predetermined distance between the second and third semiconductor regions, and having a second impurity concentration, a second-conductivity-type fourth semiconductor region formed in a surface portion of the second semiconductor region, and having a concentration higher than the second impurity concentration, an insulating film formed over the surfaces of the first, second, third, and fourth semiconductor layers, and a control electrode formed on the insulating film, wherein a junction of first and second conductivity types formed between the first semiconductor layer and the third semiconductor region is positioned below the control electrode, or below an end portion, on a side of the third semiconductor region, of the control electrode, via the insulating film.