Nonvolatile semiconductor memory device including mos transistors each having a floating gate and control gate

Abstract

A nonvolatile semiconductor memory device includes memory cells including a first MOS transistor, and a boosting circuit including a capacitor element. The first MOS transistor includes a charge accumulation layer and a control gate formed on the charge accumulation layer with an inter-gate insulating film interposed therebetween. The capacitor element includes a first and a second semiconductor layers, a capacitor insulating film, and a third semiconductor layer. The first and second semiconductor layers are formed on a semiconductor substrate and separated from each other. The capacitor insulating film is formed on the top and side of each of the first and second semiconductor layers and on the semiconductor substrate between the first and second semiconductor layers and is made of the same material as that of the inter-gate insulating film. The third semiconductor layer is formed on the capacitor insulating film and is isolated electrically from the second semiconductor layer.