The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2005

Filed:

Jun. 03, 2002
Applicants:

Albert Fazio, Los Gatos, CA (US);

Krishna Parat, Palo Alto, CA (US);

Glen Wada, Fremont, CA (US);

Neal Mielke, Los Altos Hills, CA (US);

Rex Stone, San Jose, CA (US);

Inventors:

Albert Fazio, Los Gatos, CA (US);

Krishna Parat, Palo Alto, CA (US);

Glen Wada, Fremont, CA (US);

Neal Mielke, Los Altos Hills, CA (US);

Rex Stone, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L021/8238 ;
U.S. Cl.
CPC ...
Abstract

A nonvolatile memory cell comprising a pair of spaced apart shallow trench isolation regions formed in a substrate and defining a substrate active region. A tunnel dielectric is formed on the substrate active region. A floating gate is formed on the tunnel dielectric and is self aligned between the spaced apart shallow trench isolation regions. A dielectric layer is formed on the floating gate and a control gate formed on the dielectric layer. A source region and a drain region are formed in the substrate active region on opposite sides of the floating gate.


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