The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2005
Filed:
Oct. 16, 2003
Andres Bryant, Essex Junction, VT (US);
Peter E. Cottrell, Essex Junction, VT (US);
John J. Ellis-monaghan, Grand Isle, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Jed H. Rankin, South Burlington, VT (US);
Fariborz Assaderaghi, San Diego, CA (US);
Andres Bryant, Essex Junction, VT (US);
Peter E. Cottrell, Essex Junction, VT (US);
John J. Ellis-Monaghan, Grand Isle, VT (US);
Robert J. Gauthier, Jr., Hinesburg, VT (US);
Edward J. Nowak, Essex Junction, VT (US);
Jed H. Rankin, South Burlington, VT (US);
Fariborz Assaderaghi, San Diego, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A body contact structure utilizing an insulating structure between the body contact portion of the active area and the transistor portion of the active area is disclosed. In one embodiment, the present invention substitutes an insulator for at least a portion of the gate layer in the regions between the transistor and the body contact. In another embodiment, a portion of the gate layer is removed and replaced with an insulative layer in regions between the transistor and the body contact. In still another embodiment, the insulative structure is formed by forming multiple layers of gate dielectric between the gate and the body in regions between the transistor and the body contact. The body contact produced by these methods adds no significant gate capacitance to the gate.