The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 06, 2005
Filed:
Mar. 14, 2003
Shrikant P. Lohokare, Fremont, CA (US);
Andrew D. Bailey, Iii, Pleasanton, CA (US);
David Hemker, San Jose, CA (US);
Joel M. Cook, Warrenton, VA (US);
Shrikant P. Lohokare, Fremont, CA (US);
Andrew D. Bailey, III, Pleasanton, CA (US);
David Hemker, San Jose, CA (US);
Joel M. Cook, Warrenton, VA (US);
Lam Research Corporation, Fremont, CA (US);
Abstract
A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.