The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2005
Filed:
Feb. 26, 2002
Shiro Yoshida, Tokyo, JP;
Hirokazu Tohya, Tokyo, JP;
Shiro Yoshida, Tokyo, JP;
Hirokazu Tohya, Tokyo, JP;
NEC Corporation, , JP;
Abstract
A circuit layout design method capable of an LSI circuit or an electronic printed circuit board free of electromagnetic interference is provided. The layout design method according to the invention includes a quasi-stationary circuit reduction step of deviding an entire circuit represented by a net list and a part library into a plurality of quasi-stationary closed circuits having a reduced size so that an intensity of an electromagnetic wave radiated from each of the quasi-stationary closed circuits is not more than a predetermined value; a wiring constraint condition calculation step of calculating constraint conditions for each of wirings mutually connecting the plurality of quasi-stationary closed circuits so that the intensity of the electromagnetic wave radiated from each of the wirings is not more than the predetermined value; and a layout step of laying out parts and the wirings based on the net list and the parts library so as to satisfy the constraint conditions.