The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 30, 2005
Filed:
Oct. 09, 2003
Indrajit Manna, Singapore, SG;
Keng Foo Lo, Singapore, SG;
Pee Ya Tan, Singapore, SG;
Raymond Filippi, Singapore, SG;
Indrajit Manna, Singapore, SG;
Keng Foo Lo, Singapore, SG;
Pee Ya Tan, Singapore, SG;
Raymond Filippi, Singapore, SG;
Chartered Semiconductor Manufacturing Ltd., Singapore, SG;
Agilent Technologies, Inc., Santa Clara, CA (US);
Abstract
A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.