The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Jan. 21, 2003
Tatsuya Tominari, Ome, JP;
Takashi Hashimoto, Akishima, JP;
Tomoko Jinbo, Akishima, JP;
Tsutomu Udo, Musashimurayama, JP;
Tatsuya Tominari, Ome, JP;
Takashi Hashimoto, Akishima, JP;
Tomoko Jinbo, Akishima, JP;
Tsutomu Udo, Musashimurayama, JP;
Hitachi, Ltd., Tokyo, JP;
Hitachi ULSI Sytems Co., Ltd., Tokyo, JP;
Abstract
Provided is a manufacturing method of a semiconductor device, which comprises exposing a surface of a semiconductor substrate on which a heterocrystalline layer is to be grown inside of a second emitter opening portion of a hetero-junction bipolar transistor, removing water by preheat treatment in a reducing gas atmosphere, subjecting the substrate to second heat treatment in a reducing gas atmosphere at a temperature which is higher than the preheating treatment but does not adversely affect the impurity concentration distribution of another element on the semiconductor substrate, thereby removing an oxide film formed on the surface on which the heterocrystalline layer is to be grown, and then selectively causing epitaxial growth of the heterocrystalline layer on the thus cleaned surface in the second emitter opening portion. According to the present invention, reliability of a semiconductor device having a hetero-junction bipolar transistor can be improved.