The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2005
Filed:
Jun. 14, 2004
Silke Bargstädt-franke, München, DE;
Kai Esmark, München, DE;
Harald Gossner, Riemerling, DE;
Philipp Riess, Munich, DE;
Wolfgang Stadler, München, DE;
Martin Streibl, Petershausen, DE;
Martin Wendel, Hohenbrunn, DE;
Silke Bargstädt-Franke, München, DE;
Kai Esmark, München, DE;
Harald Gossner, Riemerling, DE;
Philipp Riess, Munich, DE;
Wolfgang Stadler, München, DE;
Martin Streibl, Petershausen, DE;
Martin Wendel, Hohenbrunn, DE;
Infineon Technologies AG, Munich, DE;
Abstract
A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.