The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2005
Filed:
Mar. 22, 2002
Takamitsu Higuchi, Matsumoto, JP;
Setsuya Iwashita, Nirasaki, JP;
Hiromu Miyazawa, Toyoshina-machi, JP;
Kazumasa Hasegawa, Nagano-ken, JP;
Eiji Natori, Chino, JP;
Takamitsu Higuchi, Matsumoto, JP;
Setsuya Iwashita, Nirasaki, JP;
Hiromu Miyazawa, Toyoshina-machi, JP;
Kazumasa Hasegawa, Nagano-ken, JP;
Eiji Natori, Chino, JP;
Seiko Epson Corporation, , JP;
Abstract
The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has a superior degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved, the production yield is increased and costs are reduced. A ferroelectric memory having improved angularity in the hysteresis curve, and superior memory characteristics, production yield and costs is realized as follows. Namely, a peripheral circuit chip and a memory cell array chip are engaged onto an inexpensive assembly basesuch as glass or plastic. In memory cell array chipa ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer layer and first signal electrode. As a result, a ferroelectric memory can be realized which has improved angularity in the hysteresis curve and superior memory characteristics, production yield, and cost.