The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 16, 2005
Filed:
Feb. 18, 2003
Vijay Parthasarathy, Phoenix, AZ (US);
Vishnu Khemka, Mesa, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Amitava Bose, Tempe, AZ (US);
Todd Roggenbauer, Chandler, AZ (US);
Paul Hui, Mesa, AZ (US);
Michael C. Butner, Phoenix, AZ (US);
Vijay Parthasarathy, Phoenix, AZ (US);
Vishnu Khemka, Mesa, AZ (US);
Ronghua Zhu, Chandler, AZ (US);
Amitava Bose, Tempe, AZ (US);
Todd Roggenbauer, Chandler, AZ (US);
Paul Hui, Mesa, AZ (US);
Michael C. Butner, Phoenix, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of manufacturing a semiconductor component includes forming a first electrically insulating layer () and a second electrically insulating layer () over a semiconductor substrate (). The method further includes etching a first trench () and a second trench () through the first and second electrically insulating layers and into the semiconductor substrate, and etching a third trench () through a bottom surface of the second trench and into the semiconductor substrate. The third trench has a first portion () and a second portion () interior to the first portion. The method still further includes forming a third electrically insulating layer () filling the first trench and the first portion of the third trench without filling the second portion of the third trench, and also includes forming a plug layer () in the second portion of the third trench.