The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2005
Filed:
Jun. 29, 2001
Applicants:
Thomas D. Fletcher, Portland, OR (US);
Giao Pham, Portland, OR (US);
Inventors:
Thomas D. Fletcher, Portland, OR (US);
Giao Pham, Portland, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F001/10 ;
U.S. Cl.
CPC ...
Abstract
A clock delay circuit has a plurality of outputs to provide a sequence of clock signals that togther constitute a multistage clock. The circuit further has a delay adjustment input to adjust the timing of the clock signals for at least one of the outputs relative to the clock signals at another of the outputs. In an embodiment, the circuit has a plurality of these delay adjustment inputs. In a further embodiment, the circuit has a plurality of buffer components to delay the clock signals.