The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2005
Filed:
Jul. 14, 2004
Gaku Sugahara, Nara, JP;
Yasutoshi Kawaguchi, Kadoma, JP;
Akihiko Ishibashi, Osaka, JP;
Toshiya Yokogawa, Nara, JP;
Atsushi Matsubara, Osaka, JP;
Gaku Sugahara, Nara, JP;
Yasutoshi Kawaguchi, Kadoma, JP;
Akihiko Ishibashi, Osaka, JP;
Toshiya Yokogawa, Nara, JP;
Atsushi Matsubara, Osaka, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
A nitride semiconductor device comprising a substrate () having trenches () each formed of a cavity and peaks () formed from a group III nitride on the surface thereof; a nitride semiconductor layer () formed on the substrate (); and a nitride semiconductor multilayered structure that is formed on the nitride semiconductor layer () and has an active layer, wherein the lattice constant of the substrate () is different from that of the group III nitride substance (), the substrate () has a mask () formed from a dielectric (), the mask () is formed only on the side surfaces of the peaks (), the upper surfaces of the peaks () are exposed and the substrate () is exposed in the trenches (), a height Lof the mask () is not less than 50 nm and not more than 5000 nm, a width Lof the trench () is not less than 5000 nm and not more than 50000 nm, and an aspect ratio L/Lof the trenches () is not less than 0.001 and not more than 1.0. This structure enhances the reliability of the nitride semiconductor devices.