The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2005

Filed:

Oct. 28, 2002
Applicants:

Fumio Ootsuka, Tokorozawa, JP;

Satoshi Yamamoto, Ome, JP;

Satoshi Sakai, Yokohama, JP;

Inventors:

Fumio Ootsuka, Tokorozawa, JP;

Satoshi Yamamoto, Ome, JP;

Satoshi Sakai, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L021/302 ;
U.S. Cl.
CPC ...
Abstract

A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and silicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.


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