The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2005

Filed:

Mar. 24, 2003
Applicants:

Stanely F. Wanat, Scotch Plains, NJ (US);

Robert R. Plass, Hackensack, NJ (US);

Inventors:

Stanely F. Wanat, Scotch Plains, NJ (US);

Robert R. Plass, Hackensack, NJ (US);

Assignee:

AZ Electronic Materials USA Corp., Somerville, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B32B033/00 ; B32B009/00 ; H01L021/44 ; H01L021/48 ;
U.S. Cl.
CPC ...
Abstract

Disclosed is an assembly system for stationing a semiconductor wafer suitable for processing said wafer, said system comprising: (a) a holding block; (b) a semiconductor wafer; and (c) an aqueous adhesive composition interposed between the holding block and the semiconductor wafer. Also disclosed is a process for manufacturing a semiconductor wafer, comprising the steps of: (a) providing a holding block; (b) providing a semiconductor wafer; (c) coating either the holding block or one side of the semiconductor wafer with the foregoing aqueous adhesive composition; (d) contacting either one side of the semiconductor wafer to the coated holding block or the coated side of the semiconductor wafer to the holding block, such that the semiconductor wafer adheres to the coated holding block; (e) polishing the other side of the semiconductor wafer; and (f) removing the semiconductor wafer from the coated holding block.


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