The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2005

Filed:

Sep. 03, 2003
Applicants:

Xinghao Chen, Endwell, NY (US);

Joseph C. Watkins, Endicott, NY (US);

Inventors:

Xinghao Chen, Endwell, NY (US);

Joseph C. Watkins, Endicott, NY (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C029/00 ;
U.S. Cl.
CPC ...
Abstract

A method for improving the efficiency of test sequences for circuits with embedded multiple-port arrays, such as random access memory (RAM), is described, With existing test generation methods, it is a common occurrence that a resulting test sequence only utilizes a minimum number of read ports for detecting a target fault. When this type of test sequences is applied, one or more outputs of embedded RAMs may not attain known values, consequently reducing the effectiveness of the test sequences. The present invention enhances test sequences to that when they are applied, all outputs of embedded RAMs attain known values.


Find Patent Forward Citations

Chen, Xinghao. (2005). Test sequences generated by automatic test pattern generation and applicable to circuits with embedded multi-port rams (U.S. Patent No. 6922800). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6922800

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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